Cypress Semiconductor /psoc63 /SRSS /PWR_TRIM_PWRSYS_CTL

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Interpret as PWR_TRIM_PWRSYS_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ACT_REG_TRIM 0ACT_REG_BOOST

Description

Power System Trim Register

Fields

ACT_REG_TRIM

Trim for the Active-Regulator. This sets the output voltage level. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV. The actual output voltage will vary depending on conditions and load. The following settings are explicitly shown for convenience, and other values may be calculated using the formula: 5’h07: 900mV (nominal) 5’h17: 1100mV (nominal)

ACT_REG_BOOST

Controls the tradeoff between output current and internal operating current for the Active Regulator. The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that. This may allow a reduction in the internal operating current of the regulator. The regulator internal operating current depends on the boost setting: 2’b00: 50uA 2’b01: 100uA 2’b10: 150uA 2’b11: 200uA

The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer). The defaults are set assuming the application consumes the maximum allowed by the chip. 50mA chip: 2’b00 (default); 100mA chip: 2’b00 (default); 150mA chip: 50…100mA app => 2’b00, 150mA app => 2’b01 (default); 200mA chip: 50mA app => 2’b00, 100…150mA app => 2’b01, 200mA app => 2’b10 (default); 250mA chip: 50mA app => 2’b00, 100…150mA app => 2’b01, 200…250mA app => 2’b10 (default); 300mA chip: 50mA app => 2’b00, 100…150mA app => 2’b01, 200…250mA app => 2’b10, 300mA app => 2’b11 (default);

This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.

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